標題: Modified polycrystalline silicon chemical-vapor deposition process for improving roughness at oxide/polycrystalline silicon interface
作者: Chang, JJ
Hsieh, TE
Wang, YL
Tseng, WT
Liu, CP
Lan, CY
材料科學與工程學系
Department of Materials Science and Engineering
關鍵字: annealing;grain boundary;silicon;silicon oxide
公開日期: 24-Jan-2005
摘要: A new modified low pressure chemical-vapor deposition process for stacked polysilicon (poly-Si) films is developed in this study. The proposed stacked film process combines polysilicon with amorphous silicon films. In this process, polysilicon film was deposited first at 630degreesC, followed by a continuous temperature decrease down to 560degreesC for the deposition of amorphous silicon film. It was found that the doped stacked polysilicon films deposited by this process result in lowering of surface roughness, together with reduction of the (311) phase of the doped amorphous silicon and (110) phase of the doped polysilicon. As a consequence, device performance based on the stacked films also improves. Results of surface roughness analysis indicated that the doped stacked polysilicon film has a root-mean square surface roughness (Rrms) of 78 A, which is smaller than those of doped conventional (630degreesC) polysilicon film (Rrms=97 A), and doped amorphous silicon film (Rrms=123 A, deposited at 560degreesC). Transmission electron microscopic (TEM) observation performed at oxide/polysilicon interface showed that the conventional (630degreesC) oxide/polysilicon interface has high angle grain boundaries on the polysilicon side, which may induce leakage current around the interfacial area. (C) 2004 Elsevier B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/j.tsf.2004.06.165
http://hdl.handle.net/11536/24107
ISSN: 0040-6090
DOI: 10.1016/j.tsf.2004.06.165
期刊: THIN SOLID FILMS
Volume: 472
Issue: 1-2
起始頁: 164
結束頁: 168
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