標題: A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique
作者: Chen, Wei-Chung
Ping, Su-Yi
Huang, Tzu-Chi
Lee, Yu-Huei
Chen, Ke-Horng
Wey, Chin-Long
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: Asynchronous digital low-dropout (LDO) regulator;bidirectional asynchronous signal pipeline;dynamic voltage scaling (DVS);hybrid operation;million instructions per second performance;power conversion efficiency;power module;ripple-based control;switching regulator
公開日期: 1-三月-2014
摘要: Dual dynamic voltage scaling (DVS) techniques employed in single-inductor dual-output (SIDO) converters are used to improve the efficiency of the system-on-a-chip (SoC). One DVS technique for digital circuits is controlled by the SoC processor. This paper presents the analog DVS (ADVS) technique for analog circuits to scale voltage across the power MOSFET of the switchable digital-analog (D/A) low-dropout (LDO) regulator which is the post-regulator cascaded in series with the SIDO converter. The ADVS determines the tradeoff between voltage suppression and efficiency. Furthermore, because of the digital operation of the D/A LDO regulator, the quiescent current is further reduced at light loads while the load current requirement is minimized. In addition, the limitation of the capacitor-free LDO is significantly reduced by a few microamperes. The test chip was fabricated using a 40-nm CMOS process. Experimental results demonstrated switchable D/A LDO regulator operation with peak efficiency at 96.7% in analog operation and a 5-mV output voltage ripple at 120-mA load resulting from the advantage of ripple suppression. The power efficiency could be sustained at a value over 92.57% even when the load current decreased to 1 mu A.
URI: http://dx.doi.org/10.1109/JSSC.2013.2297395
http://hdl.handle.net/11536/24011
ISSN: 0018-9200
DOI: 10.1109/JSSC.2013.2297395
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 49
Issue: 3
起始頁: 740
結束頁: 750
顯示於類別:期刊論文


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  1. 000332765200015.pdf