標題: Simulation and Investigation of Random Grain-Boundary-Induced Variabilities for Stackable NAND Flash Using 3-D Voronoi Grain Patterns
作者: Yang, Ching-Wei
Su, Pin
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 3-D NAND;grain boundary (GB);variability;Voronoi
公開日期: 1-四月-2014
摘要: This brief investigates the random grain-boundary (GB)-induced variability in poly-crystalline silicon thin-film transistor for stackable NAND flash applications using 3-D Voronoi grain patterns. Compared with the 1-D and 2-D methods, the 3-D Voronoi grain can show a more realistic threshold-voltage variability when devices are downscaled along the channel height (Hch) direction. Therefore, a full 3-D consideration is needed when modeling the random GB-induced variation.
URI: http://dx.doi.org/10.1109/TED.2014.2308951
http://hdl.handle.net/11536/23954
ISSN: 0018-9383
DOI: 10.1109/TED.2014.2308951
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 61
Issue: 4
起始頁: 1211
結束頁: 1214
顯示於類別:期刊論文


文件中的檔案:

  1. 000333464000041.pdf