標題: Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
作者: Chiu, Po-Yen
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2014
摘要: Between the metal-insulator-metal (MIM) capacitor and metal-oxide-metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general integrated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the power-rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828 mu A to 358 nA at 25 degrees C, as compared to the traditional design with MOS capacitor in the test chip fabricated in a 65 nm CMOS process. (C) 2013 Elsevier Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/j.microrel.2013.08.011
http://hdl.handle.net/11536/23853
ISSN: 0026-2714
DOI: 10.1016/j.microrel.2013.08.011
期刊: MICROELECTRONICS RELIABILITY
Volume: 54
Issue: 1
起始頁: 64
結束頁: 70
顯示於類別:期刊論文


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  1. 000331342800010.pdf