Title: Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer
Authors: Lee, Ko-Hui
Lin, Horng-Chih
Huang, Tiao-Yuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Issue Date: 1-Jan-2014
Abstract: Gate-all-around (GAA) nanowire (NW) memory devices with a SiN- or Hf-based charge-trapping (CT) layer of the same thickness were studied in this work. The GAA NW devices were fabricated with planar thin-film transistors (TFTs) on the same substrate using a novel scheme without resorting to the use of advanced lithographic tools. Owing to their higher dielectric constant, the GAA NW devices with a HfO2 or HfAlO CT layer show greatly enhanced programming/erasing (P/E) efficiency as compared with those with a SiN CT layer. Furthermore, the incorporation of Al into the Hf-based dielectric increases the thermal stability of the CT layer, improving retention and endurance characteristics. (C) 2014 The Japan Society of Applied Physics
URI: http://dx.doi.org/10.7567/JJAP.53.014001
http://hdl.handle.net/11536/23850
ISSN: 0021-4922
DOI: 10.7567/JJAP.53.014001
Journal: JAPANESE JOURNAL OF APPLIED PHYSICS
Volume: 53
Issue: 1
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