標題: Three-dimensional metal gate-high-kappa-GOI CMOSFETs on 1-poly-6-metal 0.18-mu m Si devices
作者: Yu, DS
Chin, A
Liao, CC
Lee, CF
Cheng, CF
Li, MF
Yoo, WJ
McAlister, SP
奈米科技中心
Center for Nanoscience and Technology
關鍵字: Ge-on-insulator (GOI);LaAlO3;metal-gate;MOSFET;three-dimensional (3-D)
公開日期: 1-Feb-2005
摘要: We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.
URI: http://dx.doi.org/10.1109/LED.2004.841861
http://hdl.handle.net/11536/23667
ISSN: 0741-3106
DOI: 10.1109/LED.2004.841861
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 26
Issue: 2
起始頁: 118
結束頁: 120
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