標題: The Design and Implementation of Heterogeneous Multicore Systems for Energy-efficient Speculative Thread Execution
作者: Luo, Yangchun
Hsu, Wei-Chung
Zhai, Antonia
交大名義發表
National Chiao Tung University
關鍵字: Thread-Level Speculation;energy efficiency;heterogeneous multicore;dynamic resource allocation
公開日期: 1-十二月-2013
摘要: With the emergence of multicore processors, various aggressive execution models have been proposed to exploit fine-grained thread-level parallelism, taking advantage of the fast on-chip interconnection communication. However, the aggressive nature of these execution models often leads to excessive energy consumption incommensurate to execution time reduction. In the context of Thread-Level Speculation, we demonstrated that on a same-ISA heterogeneous multicore system, by dynamically deciding how on-chip resources are utilized, speculative threads can achieve performance gain in an energy-efficient way. Through a systematic design space exploration, we built a multicore architecture that integrates heterogeneous components of processing cores and first-level caches. To cope with processor reconfiguration overheads, we introduced runtime mechanisms to mitigate their impacts. To match program execution with the most energy-efficient processor configuration, the system was equipped with a dynamic resource allocation scheme that characterizes program behaviors using novel processor counters. We evaluated the proposed heterogeneous system with a diverse set of benchmark programs from SPEC CPU2000 and CPU20006 suites. Compared to the most efficient homogeneous TLS implementation, we achieved similar performance but consumed 18% less energy. Compared to the most efficient homogeneous uniprocessor running sequential programs, we improved performance by 29% and reduced energy consumption by 3.6%, which is a 42% improvement in energy-delay-squared product.
URI: http://dx.doi.org/10.1145/2541228.2541233
http://hdl.handle.net/11536/23647
ISSN: 1544-3566
DOI: 10.1145/2541228.2541233
期刊: ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
Volume: 10
Issue: 4
結束頁: 
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  1. 000330509300005.pdf