標題: SIMPLIFYING SEQUENTIAL-CIRCUIT TEST-GENERATION
作者: SHEU, ML
LEE, CL
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-九月-1994
摘要: Design for testability reduces testing costs for sequential circuits. The authors present a parity checker DFT scheme they have incorporated into a finite-state machine synthesis system. Generating tests for circuits synthesized according to this scheme becomes extremely simple. The derived test sequence very efficiently detects faults.
URI: http://hdl.handle.net/11536/2362
ISSN: 0740-7475
期刊: IEEE DESIGN & TEST OF COMPUTERS
Volume: 11
Issue: 3
起始頁: 28
結束頁: 38
顯示於類別:期刊論文


文件中的檔案:

  1. A1994PB47600004.pdf