標題: A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC
作者: Chang, SC
Peng, WH
Wang, SH
Chiang, T
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: H.264 de-blocking filter;loop filter;AVC
公開日期: 1-二月-2005
摘要: In this paper, we proposed a platform based bus-interleaved architecture for the de-blocking filter in H.264. Specifically, to efficiently use the bus bandwidth, we classify the filtering mode into 8 types and use an adaptive transmission scheme to avoid redundant data transfer. Moreover, to reduce the processing latency, we use a bus-interleaved architecture for conducting data transmission and filtering in parallel. As compared to the state-of-the-art designs, our scheme offers 1.6x to 7x performance improvement. While clocking at 100MHz, our design can support 2560x1280@30Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can be easily applied in system-on-chip design.
URI: http://dx.doi.org/10.1109/TCE.2005.1405728
http://hdl.handle.net/11536/23467
ISSN: 0098-3063
DOI: 10.1109/TCE.2005.1405728
期刊: IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
Volume: 51
Issue: 1
起始頁: 249
結束頁: 255
顯示於類別:期刊論文


文件中的檔案:

  1. 000227596000038.pdf