標題: Optimal Common-Centroid-Based Unit Capacitor Placements for Yield Enhancement of Switched-Capacitor Circuits
作者: Huang, Chien-Chih
Wey, Chin-Long
Chen, Jwu-E
Luo, Pei-Wen
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: Design;Algorithms;Performance;Mismatch;common centroid;spatial correlation;process variation;variance of ratio;placement optimization;yield enhancement
公開日期: 1-十二月-2013
摘要: Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.
URI: http://dx.doi.org/10.1145/2534394
http://hdl.handle.net/11536/23434
ISSN: 1084-4309
DOI: 10.1145/2534394
期刊: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
Volume: 19
Issue: 1
結束頁: 
顯示於類別:期刊論文


文件中的檔案:

  1. 000329131400007.pdf