標題: A SILICIDATION-INDUCED PROCESS CONSIDERATION FOR FORMING SCALE-DOWN SILICIDED JUNCTION
作者: CHENG, HC
JUANG, MH
LIN, CT
HUANG, LM
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-九月-1994
摘要: A process consideration for forming silicided shallow junctions, arising from silicidation process, has been discussed. The CoSi2 shallow p+n junctions formed by various schemes are characterized. The scheme that implants BF2+ ions into thin Co films on Si substrates and subsequent silicidation yields good junctions, but the problems about the dopant drive-in and knock-on of metal deeply degrade this scheme. In the regime that implants the dopant into Si and then Co deposition, however, a large perimeter leakage of 0.1 nA/cm is caused. Generation current, associated with a defect-enhanced diffusion of Co in Si during silicidation, dominates the leakage. A high-temperature pre-activation prior to Co deposition reduces the perimeter leakage to 0.038 nA/cm, but which deepens the junctions.
URI: http://dx.doi.org/10.1109/55.311128
http://hdl.handle.net/11536/2340
ISSN: 0741-3106
DOI: 10.1109/55.311128
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 15
Issue: 9
起始頁: 342
結束頁: 344
顯示於類別:期刊論文


文件中的檔案:

  1. A1994PE79800008.pdf