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dc.contributor.authorHsieh, Tien-Yuen_US
dc.contributor.authorChang, Ting-Changen_US
dc.contributor.authorChen, Te-Chihen_US
dc.contributor.authorTsai, Ming-Yenen_US
dc.contributor.authorChen, Yu-Teen_US
dc.contributor.authorJian, Fu-Yenen_US
dc.contributor.authorLin, Chia-Shengen_US
dc.contributor.authorTsai, Wu-Weien_US
dc.contributor.authorChiang, Wen-Jenen_US
dc.contributor.authorYan, Jing-Yien_US
dc.date.accessioned2014-12-08T15:33:46Z-
dc.date.available2014-12-08T15:33:46Z-
dc.date.issued2013-09-01en_US
dc.identifier.issn0257-8972en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.surfcoat.2012.10.030en_US
dc.identifier.urihttp://hdl.handle.net/11536/23332-
dc.description.abstractThis paper investigates the temperature and ambiance effects on various reliability issues for InGaZnO thin film transistors with an organic passivation layer. Hot-carrier stress and gate-bias stress are carried out under different environmental temperatures and ambient gases. The device exhibits relatively good stability under room temperture, whereas high temperature enhances degradation. Futhermore, different degradation behaviors after gate-bias stress in atmosphere and in vacuum can be attributed to gas adsorption/desorption-induced instability. Moreover, capacitance-voltage measurement techinique is utilized to analyze the degradation mechanism and to extract the density of state (DOS). The result reveals that the threshold voltage shift after both hot-carrier and gate-bias stress originates from the charge-trapping effect at the interface of gate insulator and active layer, with the extra trap states generated during stress responsible for C-V curve distortion. In addition, the asymmetric degradation behavior of gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs) indicates that trap states are generated near the drain side. (C) 2012 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectIndium Gallium Zinc Oxide (IGZO)en_US
dc.subjectThin film transistors (TFTs)en_US
dc.subjectGate-bias stressen_US
dc.subjecthot-carrier effecten_US
dc.titleInvestigation of gate-bias stress and hot-carrier stress-induced instability of InGaZnO thin-film transistors under different environmentsen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.surfcoat.2012.10.030en_US
dc.identifier.journalSURFACE & COATINGS TECHNOLOGYen_US
dc.citation.volume231en_US
dc.citation.issueen_US
dc.citation.spage478en_US
dc.citation.epage481en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000328094200100-
dc.citation.woscount0-
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