標題: ANALYSIS OF SURFACE-STATE EFFECT ON GATE LAG PHENOMENA IN GAAS-MESFETS
作者: LO, SH
LEE, CP
電控工程研究所
Institute of Electrical and Control Engineering
公開日期: 1-九月-1994
摘要: A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET's has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET's are responsible for this slow transient phenomenon. The measured ''hole-trap-like'' DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Higher gate pulse can cause more serious lag phenomenon due to larger modulation of surface charge density. Devices with shorter N+-gate spacing and lower surface state densities are shown to have less gate lag effect.
URI: http://dx.doi.org/10.1109/16.310100
http://hdl.handle.net/11536/2332
ISSN: 0018-9383
DOI: 10.1109/16.310100
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 41
Issue: 9
起始頁: 1504
結束頁: 1512
顯示於類別:期刊論文


文件中的檔案:

  1. A1994PE02600003.pdf