|標題:||Testing Retention Flip-flops in Power-gated Designs|
Chao, Mango C. -T.
Department of Electronics Engineering and Institute of Electronics
|摘要:||This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V-DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-V-DD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.|
|期刊:||2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS)|
|Appears in Collections:||Conferences Paper|