標題: Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
作者: Ker, Ming-Dou
Lin, Chun-Yu
Hsiao, Yuan-Wen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electrostatic discharge (ESD);ESD protection circuits;low capacitance;radio-frequency integrated circuit (RF IC)
公開日期: 1-六月-2011
摘要: CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.
URI: http://dx.doi.org/10.1109/TDMR.2011.2106129
http://hdl.handle.net/11536/23058
ISSN: 1530-4388
DOI: 10.1109/TDMR.2011.2106129
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 11
Issue: 2
起始頁: 207
結束頁: 218
顯示於類別:期刊論文