標題: DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOS
作者: HUANG, CY
CHEN, MJ
電子工程學系及電子研究所
電控工程研究所
Department of Electronics Engineering and Institute of Electronics
Institute of Electrical and Control Engineering
公開日期: 1-十月-1994
摘要: This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guideline has been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from guard ring.
URI: http://dx.doi.org/10.1109/16.324585
http://hdl.handle.net/11536/2300
ISSN: 0018-9383
DOI: 10.1109/16.324585
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 41
Issue: 10
起始頁: 1806
結束頁: 1810
顯示於類別:期刊論文


文件中的檔案:

  1. A1994PK41000017.pdf