標題: Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire
作者: Lee, Ko-Hui
Tsai, Jung-Ruey
Chang, Ruey-Dar
Lin, Horng-Chih
Huang, Tiao-Yuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 7-十月-2013
摘要: A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings. (C) 2013 AIP Publishing LLC.
URI: http://dx.doi.org/10.1063/1.4824817
http://hdl.handle.net/11536/22986
ISSN: 0003-6951
DOI: 10.1063/1.4824817
期刊: APPLIED PHYSICS LETTERS
Volume: 103
Issue: 15
結束頁: 
顯示於類別:期刊論文


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