標題: Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
作者: Lin, Chun-Yu
Chu, Li-Wei
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 40 Gb/s;CMOS;electrostatic discharge (ESD);high speed
公開日期: 1-十一月-2013
摘要: To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including highspeed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness.
URI: http://dx.doi.org/10.1109/TED.2013.2279408
http://hdl.handle.net/11536/22942
ISSN: 0018-9383
DOI: 10.1109/TED.2013.2279408
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 60
Issue: 11
起始頁: 3625
結束頁: 3631
顯示於類別:期刊論文


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  1. 000326263200003.pdf