Title: A Near-Threshold 480 MHz 78 mu W All-Digital PLL With a Bootstrapped DCO
Authors: Ho, Yingchieh
Yang, Yu-Sheng
Chang, ChiaChi
Su, Chauchin
交大名義發表
電機工程學系
National Chiao Tung University
Department of Electrical and Computer Engineering
Keywords: All-digital phase-locked loop (ADPLL);bootstrapped circuit;energy-efficient design;low-power;low-voltage;near-threshold circuit
Issue Date: 1-Nov-2013
Abstract: This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm(2). The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 mu W. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 mu W (2.4 mu W) under a supply voltage of 0.5 V (0.25 V).
URI: http://dx.doi.org/10.1109/JSSC.2013.2280409
http://hdl.handle.net/11536/22937
ISSN: 0018-9200
DOI: 10.1109/JSSC.2013.2280409
Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 48
Issue: 11
Begin Page: 2805
End Page: 2814
Appears in Collections:Articles


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