標題: Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
作者: Peng, Shen-Yu
Huang, Tzu-Chi
Lee, Yu-Huei
Chiu, Chao-Chang
Chen, Ke-Horng
Lin, Ying-Hsi
Lee, Chao-Cheng
Tsai, Tsung-Yen
Huang, Chen-Chih
Chen, Long-Der
Yang, Cheng-Chen
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: Buck converter;digital signal processor (DSP);dynamic voltage scaling (DVS);fast transient;low dropout (LDO) regulator;low-power design;million instructions per second (MIPS) performance;SoC;switching regulator
公開日期: 1-Nov-2013
摘要: This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-mu m standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/mu s saved 53% power.
URI: http://dx.doi.org/10.1109/JSSC.2013.2274885
http://hdl.handle.net/11536/22934
ISSN: 0018-9200
DOI: 10.1109/JSSC.2013.2274885
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 48
Issue: 11
起始頁: 2649
結束頁: 2661
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