標題: Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
作者: Altolaguirre, Federico Agustin
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electrostatic discharge (ESD);gate leakage;power-rail clamp circuit;silicon controlled rectifier (SCR)
公開日期: 1-十月-2013
摘要: A new silicon controlled rectifier-based power-rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a diode-string based level-sensing ESD detection circuit, but not using MOS capacitor, which has very large leakage current. Moreover, the leakage current on the ESD detection circuit is further reduced, adding a diode in series with the trigger transistor. By combining these two techniques, the total silicon area of the power-rail ESD clamp circuit can be reduced three times, whereas the leakage current is three orders of magnitude smaller than that of the traditional design.
URI: http://dx.doi.org/10.1109/TED.2013.2274701
http://hdl.handle.net/11536/22701
ISSN: 0018-9383
DOI: 10.1109/TED.2013.2274701
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 60
Issue: 10
起始頁: 3500
結束頁: 3507
顯示於類別:期刊論文


文件中的檔案:

  1. 000324928900074.pdf