標題: Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)
作者: Chen, Shin-Kai
Liu, Chih-Wei
Wu, Tsung-Yi
Tsai, An-Chi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Adaptive carry estimation;error compensation;speculating multiplier
公開日期: 1-十月-2013
摘要: Data hazards cause severe pipeline performance degradation for data-intensive computing processes. To improve the performance under a pessimistic assumption on the pipeline efficiency, a high-speed and energy-efficient VLSBM is proposed that successively performs a speculating and correcting phase. To reduce the critical path, the VLSBM partial products are partitioned into the (n - z)-bit least significant part (LSP) and the self-reliant (n + z)-bit most significant part (MSP), and an estimation function stochastically predicts the carry to the MSP, thereby allowing independent calculation of the partial-product accumulation of parts. When a carry prediction is accurate, the data dependence is hidden and the correcting phase is bypassed, thereby ensuring the potential speed-up of the pipelined datapath. If a prediction is inaccurate, the speculation is flushed and the correcting phase is executed to obtain the exact multiplication. The simulation results verify the effectiveness of the proposed VLSBM. When applied to a DSP algorithm with a data hazard (or dependence) probability P-D, 0 <= P-D <= 1, the results show that the proposed VLSBM outperforms the original Booth multiplier and the fastest conventional well-pipelined modified Booth multiplier when P-D > 0.32. For the case of high P-D with P-D approximate to 1, the proposed VLSBM improves approximately 1.47 times speedup against the fastest conventional pipelined Booth multiplier (@ UMC 90 nm CMOS) and, furthermore, approximately 25.4% of energy per multiplication and 7% of area are saved. By examining multiplications during three multimedia application processes (i.e., JPEG compression, object detection, and H.264/AVC decoding), the proposed VLSBM improves the speed-up ratio by approximately 1.0 to 1.4 times, and reduces the cycle count ratio by approximately 1.3 to 1.8 times in comparison to the fastest conventional two-stage pipelined Booth multiplier.
URI: http://dx.doi.org/10.1109/TCSI.2013.2248851
http://hdl.handle.net/11536/22697
ISSN: 1549-8328
DOI: 10.1109/TCSI.2013.2248851
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 60
Issue: 10
起始頁: 2631
結束頁: 2643
顯示於類別:期刊論文


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  1. 000325225700008.pdf