標題: A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
作者: CHIN, SY
WU, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十一月-1994
摘要: This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-mu m double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources, In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to +/- 1/2 LSB is within 8 ns. The chip area is 1.8 mm x 1.0 mm.
URI: http://dx.doi.org/10.1109/4.328639
http://hdl.handle.net/11536/2255
ISSN: 0018-9200
DOI: 10.1109/4.328639
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 29
Issue: 11
起始頁: 1374
結束頁: 1380
顯示於類別:期刊論文


文件中的檔案:

  1. A1994PP28400012.pdf