標題: All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle
作者: Su, Jun-Ren
Liao, Te-Wen
Hung, Chung-Chih
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: Duty-cycle setting circuit;fast-locking;programmable duty cycle;pulsewidth-control circuit
公開日期: 1-Jun-2013
摘要: This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This paper presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the two-stage matrix converter 0.18-mu m CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600 MHz, and an input duty cycle ranging from 30% to 70%. It achieves a programmable output duty cycle ranging from 31.25% to 68.75% in increments of 6.25%.
URI: http://dx.doi.org/10.1109/TVLSI.2012.2205168
http://hdl.handle.net/11536/22348
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2012.2205168
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 21
Issue: 6
起始頁: 1154
結束頁: 1164
Appears in Collections:Articles


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