標題: A 210-GHz Amplifier in 40-nm Digital CMOS Technology
作者: Ko, Chun-Lin
Li, Chun-Hsing
Kuo, Chien-Nan
Kuo, Ming-Ching
Chang, Da-Chiang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Amplifier;maximum gain;shunt stub matching;transmission line
公開日期: 1-Jun-2013
摘要: This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.
URI: http://dx.doi.org/10.1109/TMTT.2013.2260767
http://hdl.handle.net/11536/22323
ISSN: 0018-9480
DOI: 10.1109/TMTT.2013.2260767
期刊: IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Volume: 61
Issue: 6
起始頁: 2438
結束頁: 2446
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