標題: Agglomerative-Based Flip-Flop Merging and Relocation for Signal Wirelength and Clock Tree Optimization
作者: Liu, Sean Shih-Ying
Lo, Wan-Ting
Lee, Chieh-Jui
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Algorithms;Design
公開日期: 1-七月-2013
摘要: In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.
URI: http://dx.doi.org/10.1145/2491477.2491484
http://hdl.handle.net/11536/22215
ISSN: 1084-4309
DOI: 10.1145/2491477.2491484
期刊: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
Volume: 18
Issue: 3
結束頁: 
顯示於類別:期刊論文


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  1. 000322449700007.pdf