標題: HIGH-SPEED MEDIAN FILTER DESIGNS USING SHIFTABLE CONTENT-ADDRESSABLE MEMORY
作者: LEE, CY
HSIEH, PW
TSAI, JM
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十二月-1994
摘要: This paper presents a very efficient VLSI architecture for real-time median filtering as requested in many image/video applications, The median is obtained by first sorting input sequences and then selecting identified order according to the number of inputs, To reach the goal of high-speed data sorting, an optimized delete-and-insert algorithm is derived and then mapped onto shiftable content-addressable memory architecture, The complete design can be decomposed into a set of processor elements, where each processor element consists of two basic cells- sort-cell and compare-cell, Thus the design becomes very regular, More specifically any specified order can be obtained within one cycle and a high-speed clock rate can be achieved, A proto-type chip for 64 samples based on this architecture has been implemented and tested, Results show that a clock rate up to 50 MHz can be achieved using a 1.2 mu m CMOS double metal technology.
URI: http://dx.doi.org/10.1109/76.340196
http://hdl.handle.net/11536/2215
ISSN: 1051-8215
DOI: 10.1109/76.340196
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Volume: 4
Issue: 6
起始頁: 544
結束頁: 549
顯示於類別:期刊論文


文件中的檔案:

  1. A1994PZ22600004.pdf