標題: Board- and Chip-Aware Package Wire Planning
作者: Lee, Ren-Jie
Hsu, Hsin-Wu
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Chip-package-board codesign;package congestion mitigation;package wire planning
公開日期: 1-八月-2013
摘要: The slow turnaround between design, package, and system houses has been one of the primary concerns in the semiconductor business. There is a serious lag in the development time of the systems due to time-consuming interface design between the chip, package, and board. In order to enable chip-package-board codesign to speed up the design process, we propose an approach to address this issue by efficiently planning wires for board and chip design awareness, which includes the package pin-out designation and the corresponding wire planning in package and board. We model the problem as an interval intersection problem. Because of the special need in pin-out rules, an algorithm to resolve the problem is developed. We then use some optimization techniques to further improve objectives such as global wire congestion and length deviation. Our results show that a very efficient estimation can be made considering those important objectives, and package congestion can be successfully mitigated.
URI: http://dx.doi.org/10.1109/TVLSI.2012.2212288
http://hdl.handle.net/11536/22125
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2012.2212288
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 21
Issue: 8
起始頁: 1377
結束頁: 1387
顯示於類別:期刊論文


文件中的檔案:

  1. 000322380600001.pdf