標題: Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures
作者: Wu, Yi-Hong
Kuo, Po-Yi
Lu, Yi-Hsien
Chen, Yi-Hsuan
Chiang, Tsung-Yu
Wang, Kuan-Ti
Yen, Li-Chen
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
關鍵字: NH(3) plasma treatment;Ni-salicided;oxide overetching depth;polycrystalline-silicon thin-film transistors (poly-Si TFTs);vertical channel;vertical-channel Ni-salicided poly-Si TFTs (VSA-TFTs)
公開日期: 1-Jul-2011
摘要: This paper reports the impacts of NH(3) plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. OFF-state currents may be improved by increasing the oxide overetching depth. The ON/OFF current ratio may be also improved by increasing the oxide overetching depth. The NH(3) plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH(3) plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (< 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. OFF-state currents can be improved by increasing L(mask), even when the oxide overetching depth and the gate oxide thickness are changed.
URI: http://dx.doi.org/10.1109/TED.2011.2142312
http://hdl.handle.net/11536/22035
ISSN: 0018-9383
DOI: 10.1109/TED.2011.2142312
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 58
Issue: 7
起始頁: 2008
結束頁: 2013
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