標題: INTERFACE-TRAP EFFECT ON GATE INDUCED DRAIN LEAKAGE CURRENT IN SUBMICRON N-MOSFETS
作者: WANG, TH
HUANG, CM
CHANG, TE
CHOU, JW
CHANG, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十二月-1994
摘要: An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5 mu m LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress, The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of Delta I-d = A exp(-Bit/F) with a value of B-it of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.
URI: http://dx.doi.org/10.1109/16.337468
http://hdl.handle.net/11536/2192
ISSN: 0018-9383
DOI: 10.1109/16.337468
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 41
Issue: 12
起始頁: 2475
結束頁: 2477
顯示於類別:期刊論文


文件中的檔案:

  1. A1994PW50100037.pdf