標題: A CHIP SET FOR PIPELINE AND PARALLEL PIPELINE FFT ARCHITECTURES
作者: SZWARC, V
DESORMEAUX, L
WONG, W
YEUNG, CPS
CHAN, CH
KWASNIEWSKI, TA
交大名義發表
National Chiao Tung University
公開日期: 1-Dec-1994
摘要: A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2N point, pipeline FFTs. Both devices have been fabricated in 1.5 mum CMOS gate array technology.
URI: http://dx.doi.org/10.1007/BF02106450
http://hdl.handle.net/11536/2184
ISSN: 0922-5773
DOI: 10.1007/BF02106450
期刊: JOURNAL OF VLSI SIGNAL PROCESSING
Volume: 8
Issue: 3
起始頁: 253
結束頁: 265
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