標題: Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack
作者: Cheng, C. H.
Chou, K. I.
Chin, Albert
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Gate first;TiLaO;CeO2;Small EOT
公開日期: 1-Apr-2013
摘要: We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V-t) of 0.31 V. This small EOT MOSFET was achieved by employing high-kappa CeO2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-kappa SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node. (C) 2013 Elsevier Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/j.sse.2013.02.003
http://hdl.handle.net/11536/21700
ISSN: 0038-1101
DOI: 10.1016/j.sse.2013.02.003
期刊: SOLID-STATE ELECTRONICS
Volume: 82
Issue: 
起始頁: 111
結束頁: 114
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