標題: PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
作者: Yeh, Chih-Ting
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-二月-2013
摘要: A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device. (C) 2012 Elsevier Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/j.microrel.2012.09.016
http://hdl.handle.net/11536/21445
ISSN: 0026-2714
DOI: 10.1016/j.microrel.2012.09.016
期刊: MICROELECTRONICS RELIABILITY
Volume: 53
Issue: 2
起始頁: 208
結束頁: 214
顯示於類別:期刊論文


文件中的檔案:

  1. 000315614600006.pdf