Title: MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
Authors: Yang, Kai-Jiun
Tsai, Shang-Ho
Chuang, Gene C. H.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: 3GPP;802.16;fast Fourier transform (FFT);long term evolution (LTE);memory scheduling;multiple-input multiple-output (MIMO);orthogonal frequency division multiplexing (OFDM);output sorting;pipeline multipath delay commutator (MDC);WiMAX
Issue Date: 1-Apr-2013
Abstract: This paper presents an multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length. Based on the MDC architecture, we propose to use radix-N-s butterflies at each stage, where N-s is the number of data streams, so that there is only one butterfly needed in each stage. Consequently, a 100% utilization rate in computational elements is achieved. Moreover, thanks to the simple control mechanism of the MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. Since the memory requirements usually dominate the die area of FFT/inverse fast Fourier transform (IFFT) processors, the proposed scheme can effectively reduce the memory size and thus the die area as well. Furthermore, to apply the proposed scheme in practical applications, we let N-s = 4 and implement a 4-stream FFT/IFFT processor with variable length including 2048, 1024, 512, and 128 for MIMO-OFDM systems. This processor can be used in IEEE 802.16 WiMAX and 3GPP long term evolution applications. The processor was implemented with an UMC 90-nm CMOS technology with a core area of 3.1 mm(2). The power consumption at 40 MHz was 63.72/62.92/57.51/51.69 mW for 2048/1024/512/128-FFT, respectively in the post-layout simulation. Finally, we analyze the complexity and performance of the implemented processor and compare it with other processors. The results show advantages of the proposed scheme in terms of area and power consumption.
URI: http://dx.doi.org/10.1109/TVLSI.2012.2194315
http://hdl.handle.net/11536/21355
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2012.2194315
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 21
Issue: 4
Begin Page: 720
End Page: 731
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