標題: PRECISE CMOS CURRENT SAMPLE HOLD CIRCUITS USING DIFFERENTIAL CLOCK FEEDTHROUGH ATTENUATION TECHNIQUES
作者: WU, CY
CHEN, CC
CHO, JJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-1995
摘要: New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-mu m CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than +/-0.4 mu A for the input currents from -550 mu A to 550 mu A. The acquisition time for a 900-mu A step transition to 0.1% settling accuracy is 150 ns. For a 410-mu A(p-p) input at 250 kHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm(2) and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits.
URI: http://dx.doi.org/10.1109/4.350189
http://hdl.handle.net/11536/2132
ISSN: 0018-9200
DOI: 10.1109/4.350189
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 30
Issue: 1
起始頁: 76
結束頁: 80
顯示於類別:期刊論文


文件中的檔案:

  1. A1995QB39600013.pdf