標題: A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
作者: Lu, Chien-Yu
Tu, Ming-Hsien
Yang, Hao-I
Wu, Ya-Ping
Huang, Huan-Shun
Lin, Yuh-Jiun
Lee, Kuen-Di
Kao, Yung-Shin
Chuang, Ching-Te
Jou, Shyh-Jye
Hwang, Wei
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Negative bit-line (NBL);ripple bit-line (RPBL);subthreshold static random-access memory (SRAM);ultra-low voltage;9T SRAM cell
公開日期: 1-十二月-2012
摘要: This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 x 385 mu m(2) 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 degrees C. The measured total power consumption is 3.94 mu W at 0.33 V, 500 kHz, and 25 degrees C.
URI: http://dx.doi.org/10.1109/TCSII.2012.2231017
http://hdl.handle.net/11536/21303
ISSN: 1549-7747
DOI: 10.1109/TCSII.2012.2231017
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 59
Issue: 12
起始頁: 863
結束頁: 867
顯示於類別:期刊論文


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  1. 000314839100004.pdf