Title: Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
Authors: Liao, Te-Wen
Su, Jun-Ren
Hung, Chung-Chih
電機工程學系
Department of Electrical and Computer Engineering
Keywords: Low spur synthesizer;phase-locked loop (PLL);voltage-controlled oscillator (VCO)
Issue Date: 1-Mar-2013
Abstract: This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-mu m CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.
URI: http://dx.doi.org/10.1109/TVLSI.2012.2190118
http://hdl.handle.net/11536/21179
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2012.2190118
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 21
Issue: 3
Begin Page: 589
End Page: 592
Appears in Collections:Articles


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