標題: A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
作者: Fang, Bing-Nan
Wu, Jieh-Tsorng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Analog-to-digital conversion;analog digital conversion;switching circuits;calibration;digital background calibration;pipeline processing;digital bias generation
公開日期: 1-三月-2013
摘要: A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A/D conversion error caused by the low dc gain of the opamps. The biasing voltages in each opamp are automatically generated using digital circuits. This bias scheme can maintain the settling behavior of the opamp against process-voltage-temperature variations. At 300 MS/s sampling rate, the ADC consumes 26.6 mW from a 1 V supply. Its measured DNL and INL are +0.52/-0.4 LSB and +0.99/-1.65 LSB respectively. Its measured SNDR and SFDR are 55.4 dB and 67.2 dB respectively. The chip active area is 0.36 mm(2).
URI: http://dx.doi.org/10.1109/JSSC.2012.2233332
http://hdl.handle.net/11536/21176
ISSN: 0018-9200
DOI: 10.1109/JSSC.2012.2233332
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 48
Issue: 3
起始頁: 670
結束頁: 683
顯示於類別:期刊論文


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  1. 000315523500004.pdf