標題: A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver
作者: Syu, Jin-Siang
Meng, Chinchun
Wang, Chia-Ling
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: Direct-conversion receiver (DCR);low-noise amplifier (LNA);sub-harmonic mixer (SHM);vertical-NPN (V-NPN);octet-phase
公開日期: 1-二月-2013
摘要: A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-mu m CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below +/-0.2 dB/+/-1 degrees, respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply.
URI: http://dx.doi.org/10.1109/TCSI.2012.2215794
http://hdl.handle.net/11536/21023
ISSN: 1549-8328
DOI: 10.1109/TCSI.2012.2215794
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 60
Issue: 2
起始頁: 437
結束頁: 447
顯示於類別:期刊論文


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  1. 000314267000016.pdf