Title: Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN-Alumina-Nitride-Vacuum-Silicon Structure
Authors: Wu, Chun-Yu
Liu, Yen-Ting
Liao, Ta-Chuan
Yu, Ming H.
Cheng, Huang-Chung
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: Field-enhanced nanowire (FEN);high-k;poly-Si;system-on-panel (SOP);thin-film transistors (TFTs);trapping-charge memory
Issue Date: 1-Aug-2011
Abstract: High-performance poly-Si-TFT-based TiN-alumina-nitride-vacuum-silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.
URI: http://dx.doi.org/10.1109/LED.2011.2158053
http://hdl.handle.net/11536/20860
ISSN: 0741-3106
DOI: 10.1109/LED.2011.2158053
Journal: IEEE ELECTRON DEVICE LETTERS
Volume: 32
Issue: 8
Begin Page: 1095
End Page: 1097
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