標題: A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC
作者: Chai, Yun
Wu, Jieh-Tsorng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Analog-to-digital conversion;pipeline processing;switched-capacitor amplification;switching circuits
公開日期: 1-十二月-2012
摘要: A 10-bit 200-MS/s pipelined ADC was fabricated using a standard 65 nm CMOS technology. We propose a dual-path amplification technique for residue generation. We split the pipeline stage into a coarse-stage multiplying digital-to-analog converter (MDAC) and a fine-stage MDAC. The opamps for these two MDACs require different specifications. They can be designed and optimized separately. They are turned off when not in use to save power. We modify the operation of a pipeline stage to accommodate the dual-path scheme by using time-interleaving capacitor sets. Operating at 200 MS/s sampling rate, this ADC consumes 5.37 mW from a 1 V supply. It achieves a signal-to-noise-plus-distortion ratio (SNDR) better than 55 dB SNDR over the entire Nyquist band. The chip active area is 0.19 mm(2).
URI: http://dx.doi.org/10.1109/JSSC.2012.2217872
http://hdl.handle.net/11536/20844
ISSN: 0018-9200
DOI: 10.1109/JSSC.2012.2217872
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 47
Issue: 12
起始頁: 2905
結束頁: 2915
顯示於類別:期刊論文


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