標題: Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications
作者: Hsieh, Jui-Hung
Chang, Tian-Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: H.264/AVC;low power;memory bandwidth;motion estimation;video coding;VLSI architecture
公開日期: 1-一月-2013
摘要: This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data bandwidth for motion estimation under a limited bandwidth supply to fit a dynamically changing bandwidth supply. The simulation results show that our proposed algorithm can achieve 66% and 41% memory bandwidth savings while maintaining an equivalent rate-distortion performance and meeting real-time targets, when compared with conventional approaches for low-motion and high-motion D1 (704 x 576)-size video, respectively. The final implementation costs 122 K gate counts with TSMC 0.13-mu m CMOS technology and consumes 74 mW of power for D1 resolution at 30 frames/s which is 40% of that achieved in previous designs.
URI: http://dx.doi.org/10.1109/TVLSI.2011.2178439
http://hdl.handle.net/11536/20789
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2011.2178439
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 21
Issue: 1
起始頁: 33
結束頁: 42
顯示於類別:期刊論文


文件中的檔案:

  1. 000312835000004.pdf