標題: The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop
作者: Huang, Zue-Der
Wu, Chung-Yu
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: phase-locked loop (PLL);VCO;coupling current-mode injection-locked frequency divider (CCMILFD);SPR-PFD;complementary-type charge pump
公開日期: 1-八月-2011
摘要: A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-mu m 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.
URI: http://dx.doi.org/10.1587/transele.E94.C.1289
http://hdl.handle.net/11536/20760
ISSN: 0916-8524
DOI: 10.1587/transele.E94.C.1289
期刊: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E94C
Issue: 8
起始頁: 1289
結束頁: 1294
顯示於類別:期刊論文


文件中的檔案:

  1. 000293664100006.pdf