標題: HIGH-THROUGHPUT DATA COMPRESSOR DESIGNS USING CONTENT-ADDRESSABLE MEMORY
作者: LEE, CY
YANG, RY
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
關鍵字: DATA STORAGE;CONTENT ADDRESSABLE MEMORY
公開日期: 1-二月-1995
摘要: The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well known LZ77 algorithm, The architecture mainly consists of three units, namely, content addressable memory, match-logic unit, and output-stage unit, The content-address-memory unit generates a Set of hits signals which identify those positions whose symbols in a specified window are the same as the input symbol. These hits signals are then passed to the match-logic unit which determines both match length and location to form the kernel of compressed data, These two items are then passed to the output-stage unit for packetisation before being sent out. Simulation results show that, based on a 0.8 mu m CMOS process technology, a clock speed of up to 50 MHz can be achieved for a VLSI design containing a 2K buffer size. This implies that the developing data compressor chip can handle many real-life applications, such as in high-speed data storage and networking systems,
URI: http://dx.doi.org/10.1049/ip-cds:19951443
http://hdl.handle.net/11536/2070
ISSN: 1350-2409
DOI: 10.1049/ip-cds:19951443
期刊: IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS
Volume: 142
Issue: 1
起始頁: 69
結束頁: 73
顯示於類別:期刊論文


文件中的檔案:

  1. A1995QL50400013.pdf