標題: High-performance vertically stacked bottom-gate and top-gate polycrystalline silicon thin-film transistors for three-dimensional integrated circuits
作者: Lee, I-Che
Tsai, Tsung-Che
Tsai, Chun-Chien
Yang, Po-Yu
Wang, Chao-Lung
Cheng, Huang-Chung
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Three dimensional integrated circuit (3-D IC);Bottom gate (BC);Top gate (TG);Excimer laser crystallization (ELC);Thin film transistors (TFTs);Inverter
公開日期: 1-十一月-2012
摘要: The three-dimensional CMOS inverter with top-gate (TG) poly-Si thin film transistors (TFTs) vertically stacked on the bottom-gate (BC) poly-Si TFTs have been proposed to achieve high-performance characteristics via excimer laser crystallization (ELC) for the first time. Under an appropriate laser irradiation energy density, the silicon grain growth could be controlled from the sidewalls of the bottom-gate structure and thus the high-quality laterally grown poly-Si film with single perpendicular grain boundary in the channel would be formed for the BC TFTs. In addition, a simple ELC method was also utilized to the top-layered poly-Si film for TG TFTs as compared with solid-state-crystallized (SPC) ones. As a result, the field-effect mobilities of the proposed n-type BC and p-type TG TFTs could be significantly increased to be 390 and 131 cm(2)/V s, respectively, in contrast to 32.3 and 14.7 cm(2)/V s for the SPC ones, accordingly. Furthermore, such three-dimensional (3-D) TFT have also been employed to demonstrate the inverter devices and is suitable for future 3-D ICs as well as system-on-panel applications. (c) 2012 Elsevier Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/j.sse.2012.05.016
http://hdl.handle.net/11536/20675
ISSN: 0038-1101
DOI: 10.1016/j.sse.2012.05.016
期刊: SOLID-STATE ELECTRONICS
Volume: 77
Issue: 
起始頁: 26
結束頁: 30
顯示於類別:期刊論文


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