標題: Timing ECO Optimization Via Bezier Curve Smoothing and Fixability Identification
作者: Chang, Hua-Yu
Jiang, Iris Hui-Ru
Chang, Yao-Wen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Engineering change order;logic synthesis;physical design;spare cell;timing optimization
公開日期: 1-十二月-2012
摘要: Due to the rapidly increasing design complexity in modern integrated circuit design, more and more timing failures are detected at late stages. Without deferring time-to-market, metal-only engineering change order (ECO) is an economical technique to correct these late-found failures. Typically, a design might need to undergo many ECO runs in design houses; consequently, the usage of spare cells for ECO is of significant importance. In this paper, we aim at timing ECO by using as few spare cells as possible. We observe that a path with good timing is desired to be geometrically smooth. Unlike negative slack and gate delay used in most prior work, we propose a new metric of timing criticality, fixability, by considering the smoothness of timing violating paths. To measure the smoothness of a path, we use the Bezier curve as the golden path. Furthermore, in order to concurrently fix timing violations, we derive a propagation property to divide violating paths into independent segments. Based on Bezier curve smoothing, fixability identification, and the propagation property, we develop an efficient algorithm to fix timing violations. Experimental results show that we can effectively resolve all timing violations with significant speedups over the state-of-the-art works.
URI: http://dx.doi.org/10.1109/TCAD.2012.2209117
http://hdl.handle.net/11536/20598
ISSN: 0278-0070
DOI: 10.1109/TCAD.2012.2209117
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 31
Issue: 12
起始頁: 1857
結束頁: 1866
顯示於類別:期刊論文


文件中的檔案:

  1. 000311358700006.pdf