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dc.contributor.authorYeh, Chih-Tingen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:28:28Z-
dc.date.available2014-12-08T15:28:28Z-
dc.date.issued2012-12-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2012.2217970en_US
dc.identifier.urihttp://hdl.handle.net/11536/20592-
dc.description.abstractA resistor-less power-rail electrostatic discharge (ESD) clamp circuit realized with only thin-gate-oxide devices and with a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By skillfully utilizing the gate leakage current to realize the equivalent resistor in the ESD-transient detection circuit, the RC-based ESD detection mechanism can be achieved without using an actual resistor to significantly reduce the layout area in I/O cells. From the measured results, the new proposed power-rail ESD clamp circuit with an SCR width of 45 mu m can achieve 5-kV human-body-model and 400-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current of 1.43 nA at room temperature under the normal circuit operating condition with 1-V bias.en_US
dc.language.isoen_USen_US
dc.subjectElectrostatic discharge (ESD)en_US
dc.subjectgate leakageen_US
dc.subjectpower-rail ESD clamp circuiten_US
dc.subjectsilicon-controlled rectifier (SCR)en_US
dc.titleResistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2012.2217970en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume59en_US
dc.citation.issue12en_US
dc.citation.spage3456en_US
dc.citation.epage3463en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000311680400045-
dc.citation.woscount2-
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