標題: Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
作者: Yeh, Chih-Ting
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electrostatic discharge (ESD);gate leakage;power-rail ESD clamp circuit;silicon-controlled rectifier (SCR)
公開日期: 1-十二月-2012
摘要: A resistor-less power-rail electrostatic discharge (ESD) clamp circuit realized with only thin-gate-oxide devices and with a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By skillfully utilizing the gate leakage current to realize the equivalent resistor in the ESD-transient detection circuit, the RC-based ESD detection mechanism can be achieved without using an actual resistor to significantly reduce the layout area in I/O cells. From the measured results, the new proposed power-rail ESD clamp circuit with an SCR width of 45 mu m can achieve 5-kV human-body-model and 400-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current of 1.43 nA at room temperature under the normal circuit operating condition with 1-V bias.
URI: http://dx.doi.org/10.1109/TED.2012.2217970
http://hdl.handle.net/11536/20592
ISSN: 0018-9383
DOI: 10.1109/TED.2012.2217970
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 59
Issue: 12
起始頁: 3456
結束頁: 3463
顯示於類別:期刊論文


文件中的檔案:

  1. 000311680400045.pdf