標題: Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump
作者: Liao, Te-Wen
Chen, Chia-Min
Su, Jun-Ren
Hung, Chung-Chih
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: CMOS analog integrated circuits;frequency synthesizer;low spur;phase-locked loops (PLLs);sub-sampling charge pump (SSCP)
公開日期: 1-十二月-2012
摘要: This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. The loop bandwidth of the system can be adjusted by the control voltage so as to reduce the locking time. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of - 114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below - 74 dBc.
URI: http://dx.doi.org/10.1109/TCSI.2012.2206462
http://hdl.handle.net/11536/20591
ISSN: 1549-8328
DOI: 10.1109/TCSI.2012.2206462
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 59
Issue: 12
起始頁: 2815
結束頁: 2824
顯示於類別:期刊論文


文件中的檔案:

  1. 000311803300002.pdf