標題: A Low-Power DCO Using Interlaced Hysteresis Delay Cells
作者: Yu, Chien-Ying
Chung, Ching-Che
Yu, Chia-Jung
Lee, Chen-Yi
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: All-digital phase-locked loop (ADPLL);digitally controlled oscillator (DCO);interlaced hysteresis delay cell (IHDC);low power
公開日期: 1-Oct-2012
摘要: This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm(2). The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 mu W at 480- and 200-MHz output, respectively.
URI: http://dx.doi.org/10.1109/TCSII.2012.2213357
http://hdl.handle.net/11536/20452
ISSN: 1549-7747
DOI: 10.1109/TCSII.2012.2213357
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 59
Issue: 10
起始頁: 673
結束頁: 677
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